1. Field of the Invention
The present invention relates to a layout structure of electronic elements and a method for detecting an electronic element by means of addressing. In particular, the present invention relates to a high density layout structure of electronic elements and a method for detecting an electronic element in a high density layout structure by means of addressing.
2. Description of the Prior Art
In the standard semiconductor process, in order to evaluate the efficiency of each procedure and to confirm the performance of the elements after the procedures, a wafer acceptance test (WAT) is performed on the wafers. The wafer acceptance test includes electrical tests on the pads disposed around the peripheral regions of the dices. The main purposes of the wafer acceptance test are to confirm the stability of the semiconductor process as well as to enhance the yield of dices. By means of the wafer acceptance test, the quality and the stability of the wafers are somewhat ensured.
In order to carry out the test successfully, the test keys disposed around the peripheral regions of dices play an important role. For this purpose, test keys which are electrically connected to the electronic elements are formed. The test keys are usually formed on the scribe lines between the dices and electrically connected to the electronic elements through pads. The layout of the test keys are generally related to the numbers of the electrodes of the electronic elements. Depending on the numbers of the electrodes, an electronic element may be electrically connected to two to four pads.
FIG. 1 illustrates a current layout structure for test keys and electronic elements. The electronic element 10 is respectively and electrically connected to 4 pads, i.e. 21/22/23/24 respectively. In the limited area for the test pads, at most 20 pads are allowed to accommodate in a linear section, a line or a row for example, for a wafer acceptance test, and accordingly, at most 5 electronic elements 10 are arranged in a linear section. If the electronic elements have common electrodes, the number of the electronic elements may be doubled. Assume the size of the test key is 1540 μm*52.6 μm=51004 μm2, so the average area occupied by each one of the electronic element 10 is 51004/5=16200.8 μm2.
In order to lower the production cost, the critical dimension of the electronic elements in the wafer is getting smaller and smaller, so the available area for the test keys is getting smaller and smaller, too, and accordingly, insufficient. It is now an urgent issue to propose a high density layout structure for electronic elements to more economically accommodate more electronic elements to be tested in a smaller and smaller area in the test key regions for test keys.